A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior description of the IC device and translates this high-level design description into netlists at various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools.
As electronic designs become more and more complex with very little or no room for silicon recall due to prohibitive cost, designers tend to spend much time during the early design stages doing prototyping and floorplanning by, for example, performing various what-if analyses and/or manual adjustment during the floorplanning stage. When performing the what-if analyses or manual floorplan adjustments, a designer may spend a significant amount of time awaiting the results of each floorplan iteration. For example, a designer may identify a critical path that fails to meet the available slack for the path and thus need to move one or more instances connected by the path to satisfy the timing requirements. The design in this case may need to calculate the new distance after moving the one or more instances, check whether moving the one or more instances does not create additional critical path(s). The designer may often need to run additional timing commands due to the unavailability of timing information for these paths that are made critical due to the moving of the one or more instances. Once the timing or slack information or data for these additional path(s) is determined, the designer may need to determine whether one or more other components or models in the same electronic design may need to be moved to make sure that no additional paths violate the timing requirements due to the designer's moving the one or more instances in the floorplan. The designer may encounter similar issues at this stage due to the lack of timing information for one or more paths connecting these one or more other components or models. Consequently, a designer may spend up to 70% of the total design cycle time and days or even weeks during the prototyping and floorplanning stage.
Therefore, there exists a need for effective and efficient techniques for prototyping and floorplanning of electronic designs.